Memory and Thread Management on NUMA Systems

Memory and Thread Management on NUMA Systems

Introduction:

In the past, we saw a steady increase in transistor count over time due to decreasing feature sizes and more sophisticated development processes: the number of transistors on an integrated circuit doubled approximately every two years. This phenomenon, later dubbed Moore�s Law after an engineer at Intel Corporation, was found to be a reliable way to forecast development of chips as well as systems based on them. At first, these additional transistors were mainly used for increasing single core performance by raising clock frequencies, building larger caches for masking the inability of memory to keep up with CPU speed, and implementing prefetching units as well as advanced out-of-order and execution-prediction logic. For the application programmer,

things did not change in significant ways: without programmer intervention programs executed faster.

1 Introduction

2 State of the Art

3 Design & Implementation

4 Evaluation

5 Conclusion & Outlook

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